Array substrate and manufacturing method thereof and display device
US9876038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Aug 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of an array substrate comprises: forming a source and a drain of a thin film transistor on a base; forming a first insulation layer; forming an active layer of the thin film transistor; forming a second insulation layer; forming a first via hole and a second via hole in the first insulation layer and the second insulation layer above the source and the drain, by etching, and forming a third via hole and a fourth via hole in the second insulation layer above the active layer, by etching; forming a first connection line connecting the source with the active layer through the first via hole and the third via hole, a second connection line connecting the drain with the active layer and the pixel electrode through the second via hole and the fourth via hole and a pixel electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.