Dielectric layer and manufacturing method of dielectric layer, and solid-state electronic device and manufacturing method of solid-state electronic device
US9876067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Mar 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a dielectric layer having high relative permittivity with low leakage current and excellent flatness. A dielectric layer 30a according to the invention is made of multilayer oxide including a first oxide layer 31 made of oxide consisting of bismuth (Bi) and niobium (Nb) or oxide consisting of bismuth (Bi), zinc (Zn), and niobium (Nb) (possibly including inevitable impurities) and a second oxide layer 32 made of oxide of one type (possibly including inevitable impurities) selected from the group of oxide consisting of lanthanum (La) and tantalum (Ta), oxide consisting of lanthanum (La) and zirconium (Zr), and oxide consisting of strontium (Sr) and tantalum (Ta).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.