Patent · US Active

Digital synchronizer

US9876631B2 · kind B2 · utility

1Cited by

13References

14Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Remco Cornelis Herman van de Beek · Eindhoven, NL
Jos Verlinden · Wachtendonk, DE
Ghiath Al-kadi · Eindhoven, NL

Key dates

Filing date	Mar 30, 2016
Grant date	Jan 23, 2018
Priority date	—
Expiry date	Mar 30, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH04B5/20
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.