Pipelined video decoder system
US9877034B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/597
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Efficient decoding of video content that may involve intra block copy operations, such as copying pixel data from one region of a frame to another region of the same frame is described. For example, a method to decode the video content may involve identifying the video frame in which intra block copy operation is to be performed, prior to the intra block copy operation being initiated. A video decoder may prefetch the pixel data from the source region to a local buffer with low memory latency such that the source pixel data to be copied into the destination blocks in the video frame is readily available. Thus, costly, and time consuming memory access may be avoided, and in turn a video decoding pipeline may operate smoothly without any stalling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.