Dynamic set associative cache apparatus for processor and access method thereof
US9880937B2 · kind B2 · utility
1Cited by
5References
8Claims
0Family size
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Key dates
| Filing date | Jul 10, 2014 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Dec 1, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.