Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device
US9881664B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.