Analog-to-digital converter with offset calibration
US9882575B1 · kind B1 · utility
4Cited by
17References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) circuit including error correction circuitry for correcting offset drifts in an ADC, such as a successive approximation register (SAR) ADC. The offset drifts can be reduced, such as by sampling the offset following an analog-to-digital conversion and subsequently providing an error correction signal based on the sampled offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.