Flash memory device with multi-level cells and method of performing operations therein according to a detected writing patter
US9886202B2 · kind B2 · utility
3Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | May 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.