Multi-core processor using three dimensional integration
US9886275B1 · kind B1 · utility
28Cited by
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19Claims
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Key dates
| Filing date | Oct 7, 2014 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Mar 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for interconnects structures for a multi-core processor including at least two multi-core integrated circuits include forming at least two multi-core integrated circuits each on a respective substrate into a stack, disposing connections through the stack between a circuit of a first one of the at least two multi-core integrated circuits and a circuit of a second, different one of the at least two multi-core integrated circuits, the integrated circuits arranged in the stack with connections of the first one connected to a receiving pad of the second one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.