Memory system and method for error correction of memory
US9886340B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 2, 2016 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Mar 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.