Pipelined convolutional operations for processing clusters
US9886377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Feb 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.