Cache memory bypass in a multi-core processor (MCP)

US9886389B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dan P. Dumarot · Patterson, US
• Karl J. Duvalsaint · Lagrangeville, US
• Daeik Daniel Kim · San Diego, US
• Moon J. Kim · Wappingers Falls, US
• Eugene B. Risi · South Burlington, US

Key dates

• Filing date: Nov 21, 2008
• Grant date: Feb 6, 2018
• Expiry date: Mar 31, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1032
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.