Memory cell having a reduced peak wake-up current
US9886988B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2016 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a circuit includes a first switch coupled to a voltage source and a bit-line (BL). The first switch is configured to couple the BL to the voltage source to charge the BL in response to a charge control signal. A second switch is coupled to the voltage source and a complimentary bit-line (BLB) and is configured to couple the BLB to the voltage source to charge the BLB in response to the charge control signal. A control circuit is electrically coupled to each of the first switch and the second switch. The control circuit is configured to generate the charge control signal. The charge control signal is configured to control the first switch and the second switch to selectively couple the BL and the BLB to the voltage source to charge the BL and the BLB from an initial voltage to a first predetermined voltage during a first discrete charging period and from the first voltage to a second predetermined voltage during a second discrete charging period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.