Fine timing adjustment method
US9887552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention may provide non-invasive techniques for adjusting timing in multistage circuit systems. A multistage circuit system according to embodiments of the present invention may include a plurality of circuit stages coupled to signal lines that carry signals. The system may also include a plurality of load circuits, one provided in for each circuit stage. The load circuits may have inputs coupled to the signal lines that carry the input signals. Each load circuit may include a current source programmable independently of the other load circuits that propagates current through an input transistor in the respective load circuit that receives the signal. The current propagating through the input transistor may provide a load on the corresponding signal line, allowing fine timing adjustment for each circuit stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.