Clock generating apparatus and clock data recovering apparatus
US9887830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2017 |
| Grant date | Feb 6, 2018 |
| Priority date | — |
| Expiry date | Jan 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.