Non-temporal write combining using cache resources
US9892039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.