Multi-channel cache memory
US9892047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2009 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory including: a plurality of parallel input ports configured to receive, in parallel, memory access requests wherein each parallel input port is operable to receive a memory access request for any one of a plurality of processing units; and a plurality of cache blocks wherein each cache block is configured to receive memory access requests from a unique one of the plurality of input ports such that there is a one-to-one mapping between the plurality of parallel input ports and the plurality of cache blocks and wherein each of the plurality of cache blocks is configured to serve a unique portion of an address space of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.