Electrostatic discharge protection circuitry
US9893517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2014 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Apr 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.