Multi-level step-up converter topologies, control and soft start systems and methods
US9893622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2017 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1584
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-level, step-up converter circuit includes an inductor including one terminal in communication with an input voltage supply. N transistor pairs are connected in series, where N is an integer greater than one. First and second transistors of a first pair of the N transistor pairs are connected together at a node. The node is in communication with another terminal of the inductor. Third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively. (N−1) capacitors have terminals connected between the N transistor pairs, respectively. An output capacitor has a terminal in communication with at least one transistor of the N transistor pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.