Power filtering circuit and method
US9893701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2001/0085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power filter circuit is provided for use in a package substrate for integrated circuits. A first power isolation circuit, having a first inductance, is configured to isolate power provided to one or more die connectors for provision to an integrated circuit die. A second power isolation circuit, having a second inductance, is configured to isolate power provided to one or more printed circuit board (PCB) connectors for provision to a PCB. A power plane electrically connects a first end of the first power isolation circuit to a first end of the second power isolation circuit, forming a “π” power filtering structure in some embodiments. A de-coupling capacitor can be provided as a surface-mount capacitor, or as an embedded capacitor in a core layer of an integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.