Multi-stage overload protection scheme for pipeline analog-to-digital converters
US9893737B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2017 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jan 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a series of analog-to-digital converter (ADC) stages and a comparison circuit coupled to a first ADC stage. The first ADC stage may be configured to compare an input signal to one or more conversion thresholds to generate a result. The first ADC stage may also be configured to generate an output signal based on a value of the result. In response to an assertion of a reset signal, the first ADC stage may be configured to set a level of the output signal voltage to a particular voltage. The comparison circuit may be configured to assert the reset signal in response to a determination that the input signal voltage exceeds an operating range defined by an upper overload threshold voltage and a lower overload threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.