Method for retaining clock traceability over an asynchronous interface
US9893826B2 · kind B2 · utility
0Cited by
1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jan 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40045
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Network elements within a network are configured to retain clock traceability over an asynchronous interface. The network elements can generate and process multi-frames that include two different types of traffic, each synchronized to a different respective clock source. Each of the multi-frames is synchronized to the clock source of one of the traffic types and further includes a timestamp to enable the original clock signal of the other traffic type to be reconstructed at the receiving network element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.