Thin film transistor array substrate and liquid crystal display panel using same
US9897877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134318
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array substrate includes a base, a first metal layer having a gate electrode and a first insulating layer covering the base and the first metal layer. A semiconductor layer is formed on the first insulating layer facing but insulated from the gate electrode. The first insulating layer also supports a second metal layer having a source electrode and a drain electrode. A pixel electrode layer is electrically coupled to the source electrode or the drain electrode. A common electrode layer is insulated from the pixel electrode and is configured to receive a common voltage. A transparent conductive layer is formed on the base and is insulated from the pixel electrode. The semiconductor layer, electrically coupled to the source electrode and the drain electrode, is located between the source electrode and the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.