Fractional divider using a calibrated digital-to-time converter
US9897976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2017 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/82
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.