Packed finite impulse response (FIR) filter processors, methods, systems, and instructions
US9898286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Sep 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.