Detecting byte ordering type errors in software code
US9898386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.