Modeling memory in emulation based on cache
US9898563B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Feb 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.