Nonvolatile memory device and method of programming the same
US9899097B2 · kind B2 · utility
2Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Dec 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.