Raid decoding architecture with reduced bandwidth
US9899104B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Apr 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.