Systems and methods for low voltage secure digital (SD) interfaces
US9899105B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 2013 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.