Semiconductor package structure
US9899305B1 · kind B1 · utility
12Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Apr 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.