Auxiliary self-protecting transistor structure
US9899370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Apr 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/813
Abstract
This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.