Three-dimensional semiconductor memory device and method for fabricating the same
US9899411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
Abstract
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.