Level shift circuit
US9900009B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Aug 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.