Method and apparatus to minimize switching noise disturbance
US9904309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | May 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.