Patent · US Active

Layout of interconnect lines in integrated circuits

US9904754B2 · kind B2 · utility

0Cited by

7References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Gerhard Hellner · Lenggries, DE
Iris Maria Leefken · Waldenbuch, DE
Silke Penth · Holzgerlingen, DE
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Jun 29, 2016
Grant date	Feb 27, 2018
Priority date	—
Expiry date	Jun 29, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.