Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs
US9904756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.