FPGA matrix architecture
US9904931B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Sep 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q10/1097
- WIPO fieldIT methods for management
- WIPO sectorElectrical engineering
Abstract
High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.