Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof
US9905315B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2017 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.