Patent · US Active

Method for producing a semi-conductor arrangement and corresponding semi-conductor arrangement

US9905533B2 · kind B2 · utility

0Cited by
5References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 8, 2015
Grant dateFeb 27, 2018
Priority date
Expiry dateJul 8, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3512
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for producing a semiconductor arrangement, said method includes fastening a semiconductor on a base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar; and perforating a region of the base element, which directly contacts the sinter, wherein the perforating includes generating a plurality of through-openings having a closed border in the region of the base element for adjusting a stiffness of at least a portion of the base element in a targeted manner

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.