Patent · US Active

Multi-voltage complementary metal oxide semiconductor integrated circuits based on always-on N-well architecture

US9905560B2 · kind B2 · utility

2Cited by
2References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 30, 2015
Grant dateFeb 27, 2018
Priority date
Expiry dateJan 7, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/951

Abstract

Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.