Semiconductor device having buried gate structure and method of fabricating the same
US9905659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Feb 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.