Method for manufacturing a monolithic silicon wafer comprising multiple vertical junctions
US9905716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Feb 4, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention relates to a method for manufacturing a monolithic silicon wafer (10) comprising multiple vertical junctions (2) having an alternation of n-doped areas and p-doped areas, including at least the steps of: (i) providing a liquid bath (100) including silicon, at least one n-type doping agent and at least one p-type doping agent; (ii) proceeding to directionally solidify the silicon in a direction (I), varying the convection-diffusion parameters thereof in order to alternate the growth of n-doped silicon layers (101) and p-doped silicon layers (102); and (iii) cutting a slice (104), parallel to the direction (I), of the multi-layer structure obtained at the end of the step (ii), such as to obtain said expected wafer (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.