Clock and data recovery circuit and method
US9906231B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.