Method for optimizing management of standby of a microprocessor enabling the implementation of several logical cores and computer program implementing such a method
US9910474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2011 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Feb 24, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject of the invention is in particular the optimization of standby management of a part of a microprocessor allowing implementation of at least two logic cores, said at least one microprocessor comprising means for placing at least one resource non common to said at least two logic cores on standby. After having determined (400) a desired standby state for each of said at least two logic cores, said desired standby state of one of said at least two logic cores is compared with the said desired standby state of the other of said at least two logic cores. In response to said comparison, instructions preparing for said placement on standby and/or allowing the restoration of said one of said at least two logic cores are launched (420).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.