Processor core power event tracing
US9910475B2 · kind B2 · utility
46Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Aug 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.