End of life extension of solid state memory
US9910606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Mar 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.