Vector operation core and vector processor
US9910671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2014 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jul 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.