Reconfigurable microprocessor hardware architecture
US9910673B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Apr 17, 2017 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Apr 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2015/768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.