Semiconductor memory devices including asymmetric word line pads
US9911750B2 · kind B2 · utility
6Cited by
1References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 15, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jan 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.